A number of memory devices, such as flash memory devices, use analog memory cells to store data. Each memory cell stores an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In flash memory devices, for example, each analog memory cell typically stores a certain voltage. The range of possible analog values for each cell is typically divided into threshold regions, with each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired one or more bits.
Single-level cell (SLC) flash memory devices, for example, store one bit per memory cell (or two possible memory states). Multi-level cell (MLC) flash memory devices, on the other hand, store two or more bits per memory cell (i.e., each cell has four or more programmable states). In a multi-level cell flash memory device, the amount of current or voltage is detected, rather than just the presence or absence of a current or voltage. In a multi-level cell device, at least three threshold levels are employed to define four or more different threshold states. The operating range of an individual cell is thus divided into an increased number of states and the range of each state is smaller than for a single-level cell device. Thus, the reliability of any single bit in a multi-level cell device is lower than a single-level cell device. For a more detailed discussion of multi-level cell (MLC) flash memory devices, see, for example, K. Takeuchi et al, “A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory with 10-MB/s Program Throughput,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 1, 219-232 (2007), and K.-T. Park et al., “A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, 919-928 (2008), each incorporated by reference herein.
Existing flash devices employ page level access techniques, whereby a page is the minimum unit that can be written to or read from the flash memory device. Pages are generally written and read independently from each other. In addition, existing flash memories typically use the same code and code rate to encode (and decode) all pages. Operating systems typically employ data sectors comprised of, for example, 512 bytes of user information. In general, the user data length is a multiple of the sector size. With one typical flash memory configuration, one page comprises eight sectors of user information. Thus, with page level access techniques, the flash controller combines eight sectors of information to write each page to the flash memory device. Each time a sector is read from the flash memory device, a full page is read that contains the desired sector.
A need exists for improved multi-level coding and read/write access techniques for multi-level cell (MLC) flash memory devices to achieve, for example, lower error rates or to improve the storage capacity. A further need exists for improved read/write access techniques for multi-level cell flash memory devices that allows a single sector to be stored across a plurality of pages in the flash memory device. Yet another need exists for improved read/write access techniques that provide per-page control of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding. For a more detailed discussion of multi-level codes, see, for example, U. Wachsmann et al., “Multilevel Codes: Theoretical Concepts and Practical Design Rules,” IEEE Trans. on Information Theory, Vol. 45, No. 5, 1361-91 (1999), incorporated by reference herein.